this document is for maintenance purposes only and is not recommended for new designs
july 1994 ds2177-2.1 mv95408 50mhz 8-bit cmos video dac the mv95408 is a cmos 8-bit, 50mhz digital to analog converter, designed for use in both video graphics and general digital television applications. a very low external component count has been achieved by including the loop ampli?r and reference voltage source on chip. the device contains a data input register and registered video controls (blank , refwhite , o verbr t and sync ). these control inputs and associated internal circuitry allows the mv95408 to be used in video graphics systems by providing the necessary video pedestal levels. the strd a c input allows the video pedestals to be disabled in conventional dac applications. this device is capable of directly driving 75 w lines with standard rs-343a or rs-170 video levels, using the appropriate r set external resistor. pull up resistors have been added to tie all unused control inputs into their inactive (high) states. features n low power consumption (180mw typ) n 50mhz pipeline operation n 1 lsb differential linearity error n 1 lsb integral linearity error n rs-343a/rs-170 compatible levels n on chip reference voltage source n guaranteed monotonic n drives 75 w loads directly n single 5v power supply ordering information mv95408 bdp (industrial - plastic dil package) mv95408 bmp (industrial - miniature plastic dil package) 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 blank v dd strd a c i out gnd 0verbr t refwhite 9 10 12 11 r set clk msb d 7 d 6 d 5 d 4 sync i out v ref d 3 d 2 d 1 lsb d 0 dp20 mp20 fig.1 pin connections - top view fig.2 block diagram of mv95408 applications n data conversion (general) n computer graphics n waveform synthesis n commercial tv n instrumentation absolute maximum ratings (reference to gnd) dc supply voltage, v dd -0.3 to +7v digital input voltage -0.3 to v dd +0.3v analog output short circuit duration inde?ite ambient operating temperature -40 c to +85 c storage temperature range -55 c to +125 c
mv95408 2 electrical characteristics these characteristics are guaranteed over the following conditions (unless otherwise stated): as speci?d in recommended operating conditions. full temperature range = -40 c to +85 c 144424443 max clock rate clock high time clock low time data and control setup time data and control hold time analog output delay analog output rise/fall time analog output settling time glitch energy v dd supply current f max t clkh t clkl t su t h t dly t rf t s idd full 25 25 25 25 25 25 25 25 25 50 7 7 6 2 10 3 15 100 30 42 6 mhz ns ns ns ns ns ns ns pv-sec ma ma maximum guaranteed freq. fc = 15mhz fc = 50mhz parameter symbol temp ( c) min. value typ. max. units conditions ac characteristics (refer to fig. 3) thermal characteristics recommended operating conditions r load (i out and i out )75 w v dd 5.0v 0.5v r set (graphics applications) 1.8k w r set (straight dac applications) 1.2k w thermal resistance dp mp chip to case q jc 20 30 c/w chip to ambient q ja 75 93 c/w dc characteristics parameter symbol temp ( c) min. value typ. max. units conditions resolution integral linearity error differential linearity error gain error inl dnl full 25 full 25 full 25 8 0.5 0.5 1% 1 1 5% bits lsb lsb lsb lsb % of full scale analog output grey scale current range 10% over bright level relative to white level white level relative to blank level black level relative to blank level white level relative to black level blank level sync level lsb size output compliance lsb v oc 25 25 25 25 25 25 25 25 25 26 275 20 107 -0.3 8.8 255 27 10 276 100 21 7.5 255 92.5 111 40 0 2.58 28 277 22 115 +1.5 ma lsb lsb ire lsb ire lsb ire lsb ire lsb ire lsb mv v 75 w singly terminated load r set = 1.8k w (graphics mode) digital inputs high level i/p voltage low level i/p voltage high level i/p current low level i/p current internal voltage reference (v ref ) v ref temperature coef?ient v ih v il i ih i il v ref 25 25 25 25 25 full 3 gnd-0.3 0.95 0.90 1.0 40 v dd +0.3 1.2 +1 -1 1.05 1.10 v v m a m a v v ppm/ c
mv95408 3 circuit description as illustrated in the function block diagram, fig. 2, the mv95408 contains an 8-bit d-to-a converter, input registers, a loop ampli?r and voltage reference. on the falling edge of each clock cycle, as shown in fig. 3, eight data bits are latched into the device and passed to the 8-bit d-to-a converter. also latched on the falling edge of the clock signal, the sync and blank inputs add the necessary weighted currents to the analog outputs to produce the required output levels for use in video applications. table 1 details how the sync , blank , refwhite and o verbr t inputs modify the dac output levels. to obtain a high data throughput rate, the decoding logic of the mv95408 is fully pipelined. this introduces a one clock cycle delay between the latching of the input data and the resultant dac output. it also ensures synchronisation of the internal data and a minimal output glitch energy. the dac employed by the mv95408 eliminates the need for precision component ratios by using a segmented architecture in which equal weight bit currents are either routed to i out or i out . the use of identical current sources and current steering their outputs means that monotonicity is guaranteed. the mv95408 eliminates the need for an external voltage reference by providing a nominally 1.0v reference on chip. an on-chip loop ampli?r also provides stability of the full scale output current against power supply and temperature variations. the full scale output current is set by an external resistor r set . by adjustment of this value it is possible to implement rs-343a or rs-170 video levels as explained in the application notes. table 1: video output truth table fig.3 timing diagram description strd a c sync blank refwhite o verbr t output data i out (lsb) refwhite + 10% 1 1 1 0 0 x 414 refwhite 1 1 1 0 1 x 387 full white 1 1 1 1 1 $ff 387 overbright 1 1 1 1 0 data data + 132 + 27 full black 1 1 1 1 1 $00 132 blank 1 1 0 x x x 111 data-sync 1 0 1 1 1 data data + 21 sync 1 0 0 x x x 0 strdac mode 0 x 1 1 x data data
mv95408 4 pin name description 2 clk the clock input. the falling edge of the clock latches the d a t a , blank , sync , o verbr t and refwhite inputs into the logic pipeline. the decoded data will be latched into the dac output 1 clock cycle later. the clock frequency determines the update rate of the dac output. 3-10 d 7 -d 0 the data inputs. d 0 is the least significant bit (lsb). the coding is in straight binary only. 13,15 i out , i out the current output and its complement. these are the high impedance current source outputs of the dac capable of driving a 75 w load up to a voltage of 1.5v. 14 gnd analog ground for the dac. 20 v dd analog power for the dac 11 v ref the output of the internal voltage reference generator. this output is nominally 1v, and should be decoupled with a 10nf capacitor. 12 r set the full scale adjust control. the r set resistor is connected from this pin to ground. an internal loop amplifier adjusts a reference current flowing through the r set resistor so that the voltage across the resistor is equal to the v ref voltage. this reference current has a weighting equal to 16 lsb?. 1 blank the composite blank control input. a logical zero on this input removes the black pedestal from the i out output, whilst forcing the internal data to the dac to $00. this input is latched on the clock falling edge and will override the refwhite and overbrt inputs. the black pedestal is 7.5 ire units (actually 21 lsb?). if left open circuit this input is internally tied high. 17 sync the composite sync control input. a logical zero on this input removes the blank pedestal from the i out output. the blank pedestal is nominally 40 ire units (actually 111 lsb?). the sync input does not override any other control lines. this input is latched on the clock falling edge. if left open circuit this input is internally tied high. 19 refwhite the reference white level control input. a logical zero on this input overrides the input data, forcing the data to $ff. the blank input will override this input. if left open circuit this input is internally tied high. 18 o verbr t the 10% overbright control input. a logical zero on this input switches the overbright pedestal into the i out output. the overbright pedestal is 10 ire units (actually 27 lsb?). this input does not override any other input. the blank input overrides this input. if left open circuit this input is internally tied high. 16 strd a c the straight dac control input. a logical zero on this input causes the black, blank and overbright pedestals to be disabled, removing them from both i out and i out . this allows the dac contribution to the output to be extended to a full 1 volt. to obtain this extra dac range, it is necessary to reduce the r set resistor value, see application notes. the blank the refwhite inputs may still be used to force the input data to $00 or $ff respectively. with the strdac pin held low the output current can be calculated from: output current = data x 1 lsb where 1 lsb= full scale = 255 lsb v ref = 1.0v typ. the exact value of 1 lsb must be calculated from the full scale output. if left open circuit this input is internally tied high and the device will be configured for video graphics. in this mode the output current can be calculated from: output current = (data + 21 + 111) x 1 lsb v ref = 1.0v typ. v ref 16 x r set
mv95408 5 applications information rs-343a and rs-170 video generation for generation of rs-343a compatible video levels (see fig.4) it is recommended that a singly terminated 75 w load be used with an r set resistor value of approximately 1.82k w similarly for the generation of rs-170 video levels a singly terminated 75 w load should be used but in association with an r set value of approximately 1.29k w to provide the increased voltage range. non-video applications the mv95408 may be used in non-video applications as explained in the pin description for strd a c mode.the relationship between r set and the full scale output current has been explained previously and for a singly terminated 75 w load an r set resistor value of approximately 1.19k w should be used. pcb layout considerations the pcb layout should provide low noise on the mv95408 power and ground lines by shielding the digital inputs and providing adequate decoupling. the pcb should utilise both power and ground planes for best performance, connecting both planes to their respective regular pcb planes through a ferrite bead located as close as possible to the device. for best performance, a 100nf capacitor should be used to decouple the reference and supply pins. decoupling should take place as close to the device as possible to reduce lead inductance. the digital inputs to the device should be isolated as much as possible from the analog outputs and other analog circuitry and should not overlay the analog ground and power planes. to reduce noise pick-up, long clock lines to the device should be avoided. for best performance the analog output should have a 75 w load connected to analog ground. fig.4 composite video output waveform fig.5 applications/test board mv95408
mv95408 6 headquarters operations gec plessey semiconductors cheney manor, swindon, wiltshire, united kingdom. sn2 2qw tel: (01793) 518000 fax: (01793) 518411 gec plessey semiconductors p.o. box 660017, 1500 green hills road, scotts valley, california 95067-0017, united states of america. tel (408) 438 2900 fax: (408) 438 5576 customer service centres france & benelux les ulis cedex tel: (1) 64 46 23 45 fax: (1) 64 46 06 07 germany munich tel: (089) 3609 06-0 fax: (089) 3609 06-55 ?italy milan tel: (02) 66040867 fax: (02)66040993 japan tokyo tel: (03) 5276-5501 fax: (03) 5276-5510 north america scotts valley, usa tel: (408) 438 2900 fax: (408) 438 7023 ?south east asia singapore tel: (65) 3827708 fax: (65) 3828872 ?sweden stockholm tel: 46 8 702 97 70 fax: 46 8 640 47 36 ?taiwan, roc taipei tel: 886 2 5461260 fax: 886 2 7190260 ? uk, eire, denmark, finland & norway swindon tel: (01793) 518510 fax: (01793) 518582 these are supported by agents and distributors in major countries world-wide. ?gec plessey semiconductors 1994 publication no.ds2177 issue no. 2.1 july 1994 technical documentation - not for resale. printed in united kingdom this publication is issued to provide information only which (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. no warranty or guarantee express or implied is mad e regarding the capability, performance or suitability of any product or service. the company reserves the right to alter without prior knowledge the speci?ation, design or price of any product or service. inform ation concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a speci? piece of equipment. it is the user's respon sibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. these products are not s uitable for use in any medical products whose failure to perform may result in signi?ant injury or death to the user. all products and materials are sold and services provided subject to the company's cond itions of sale, which are available on request.
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